64.7.9 QSPI Serial Clock Register

This register can only be written if the WPEN bit is cleared in the QSPI Write Protection Mode Register.

Name: QSPI_SCR
Offset: 0x20
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 DLYBS[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
       CPHACPOL 
Access R/WR/W 
Reset 00 

Bits 23:16 – DLYBS[7:0] Delay Before QSCK

This field defines the delay from QCS valid to the first valid QSCK transition.

When DLYBS is set to zero, the QCS valid to QSCK transition is half the QSCK clock period.

Otherwise, the following equation determines the delay:
  • DLYBS = Delay Before QSCK × fGCLK

Bit 1 – CPHA Clock Phase

CPHA determines which edge of QSCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between host and client devices.
ValueDescription
0 Data is captured on the leading edge of QSCK and changed on the following edge of QSCK.
1 Data is changed on the leading edge of QSCK and captured on the following edge of QSCK.

Bit 0 – CPOL Clock Polarity

CPOL is used to determine the inactive state value of the serial clock (QSCK). It is used with CPHA to produce the required clock/data relationship between host and client devices.
ValueDescription
0 The inactive state value of QSCK is logic level zero.
1 The inactive state value of QSCK is logic level one.