64.7.1 QSPI Control Register
This register can only be written if the WPCREN bit is cleared in the QSPI Write Protection Mode Register.
| Name: | QSPI_CR |
| Offset: | 0x00 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| LASTXFER | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RTOUT | STTFR | UPDCFG | |||||||
| Access | W | W | W | ||||||
| Reset | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWRST | SRFRSH | STPCAL | DLLOFF | DLLON | QSPIDIS | QSPIEN | |||
| Access | W | W | W | W | W | W | W | ||
| Reset | – | – | – | – | – | – | – |
Bit 24 – LASTXFER Last Transfer
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The chip select is deasserted after the end of character transmission. |
Bit 10 – RTOUT Reset Time-out
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Request a TOUT flag reset. |
Bit 9 – STTFR Start Transfer
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Starts the transfer when TFRTYP=0 and SMRM=1 or when DATAEN=0. |
Bit 8 – UPDCFG Update Configuration
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Requests an update of the QSPI Controller core configuration. |
Bit 7 – SWRST QSPI Software Reset
DMA channels state, DLL state (see DLL) and QSPI_PADCTRL are not affected by a software reset.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Resets the QSPI. A software reset of the QSPI interface is performed. |
Bit 5 – SRFRSH Start Refresh
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Starts a refresh sequence. QSPI_ISR.RFRSHD indicates when the refresh sequence is over. |
Bit 4 – STPCAL Start Pad Calibration
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Starts a QSPI pad calibration. QSPI_SR.CALBSY indicates the state of the calibration. |
Bit 3 – DLLOFF DLL Off Request
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the DLL. When the DLL is not locked (using QSPI_SR.DLOCK), the QSPI core does not receive a clock and is not functional. |
Bit 2 – DLLON DLL On Request
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the DLL. When the DLL is locked (using QSPI_SR.DLOCK), the QSPI core receives a clock and is functional. |
Bit 1 – QSPIDIS QSPI Disable
As soon as QSPIDIS is set, the QSPI finishes its transfer.
All pins are set in Input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the QSPI is disabled.
If QSPIEN and QSPIDIS are set to 1 when QSPI_CR is written, the QSPI is disabled.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the QSPI. |
Bit 0 – QSPIEN QSPI Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the QSPI. |