64.7.17 QSPI Refresh Register

This register can only be written if the WPEN bit is cleared in the QSPI Write Protection Mode Register.

Name:	QSPI_REFRESH
Offset:	0x50
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	REFRESH[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	REFRESH[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	REFRESH[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	REFRESH[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – REFRESH[31:0] Refresh Delay Counter

Defines in GCLK clock periods the delay between two refreshes of analog blocks. See Refresh Sequence.

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