64.7.2 QSPI Mode Register


Bit	31	30	29	28	27	26	25	24
	DLYCS[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DLYBCT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
			AQICMEN		NBBITS[3:0]
Access			R/W		R/W	R/W	R/W	R/W
Reset			0		0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TAMPCLR		CSMODE[1:0]		DQSDLYEN	WDRBT		SMM
Access	R/W		R/W	R/W	R/W	R/W		R/W
Reset	0		0	0	0	0		0

Bits 31:24 – DLYCS[7:0] Minimum Inactive QCS Delay

This field defines the minimum delay between the deactivation and the activation of QCS. The DLYCS time ensures the client minimum deselect time is respected.

If DLYCS is written to 0, one GCLK period is inserted by default.

Otherwise, the following equation determines the delay:

DLYCS=Minimum inactive × f_GCLK

Bits 23:16 – DLYBCT[7:0] Delay Between Consecutive Transfers

SMM=0
This field defines the delay between two consecutive transfers without releasing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.
The following equation determines the delay:
- DLYBCT=(Delay Between Consecutive Transfers × f_GCLK) / 32
SMM=1
This field defines the delay between last QSCK pulse and QCS rise.
When DLYBCT is written to 0, no delay is inserted and the clock keeps its duty cycle over the character transfers.
The following equation determines the delay:
- DLYBCT=Delay Between Consecutive Transfers × f_GCLK

Bit 13 – AQICMEN QSPI Inter-Chip Communication Mode Enable All

Value	Name	Description
0	DISABLED	The QSPI Inter-Chip mode is disabled.
1	ENABLED	The QSPI Inter-Chip mode is enabled.

Bits 11:8 – NBBITS[3:0] Number of Bits per Transfer

NBBITS is used only when SMM is set to '0'.

Value	Name	Description
0	8_BIT	8 bits for transfer
8	16_BIT	16 bits for transfer

Bit 7 – TAMPCLR Tamper Clear Enable

Value	Description
0	A tamper detection event has no effect on QSPI scrambling keys.
1	A tamper detection event immediately clears QSPI scrambling keys.

Bits 5:4 – CSMODE[1:0] Chip Select Mode

The CSMODE field determines how the chip select is deasserted.

This field is forced to LASTXFER when SMM is written to 1 and QSPI_IFR.PROTYP is not selecting a RAM memory.

Value	Name	Description
0	NOT_RELOADED	The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer.
1	LASTXFER	The chip select is deasserted when the bit LASTXFER is written to 1 and the character written in QSPI_TDR.TD has been transferred.
2	SYSTEMATICALLY	The chip select is deasserted systematically after each transfer.

Bit 3 – DQSDLYEN DQS Delay Enable

Value	Name	Description
0	DISABLED	The DQS Delay cell is disabled.
1	ENABLED	The DQS Delay cell is enabled. The DQS Delay cell automatic refresh is triggered according to the QSPI_REFRESH configuration.

Bit 2 – WDRBT Wait for Data Read Before Transfer

Value	Name	Description
0	DISABLED	No effect. In SPI mode, a transfer can be initiated whatever the state of QSPI_RDR is.
1	ENABLED	In SPI mode, a transfer can start only if QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception.

Bit 0 – SMM Serial Memory Mode

Value	Name	Description
0	SPI	The QSPI is in SPI mode.
1	MEMORY	The QSPI is in Serial Memory mode.

Name:	QSPI_MR
Offset:	0x04
Reset:	0x00000000
Property:	Read/Write