64.7.20 QSPI Pad Calibration Configuration Register
This register can only be written if the WPEN bit is cleared in the QSPI Write Protection Mode Register.
This register is not affected by a software reset (QSPI_CR.SWRST).
| Name: | QSPI_PCALCFG |
| Offset: | 0x5C |
| Reset: | 0x00000070 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CALN[3:0] | CALP[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CALCNT[8] | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CALCNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKDIV[2:0] | DIFFPM | DAPCAL | AAON | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 1 | 1 | 0 | 0 | 0 | |||
Bits 31:28 – CALN[3:0] Calibration Code for N-channel (Read-only)
Bits 27:24 – CALP[3:0] Calibration Code for P-channel (Read-only)
Bits 16:8 – CALCNT[8:0] Pad Calibration Counter
Bits 6:4 – CLKDIV[2:0] Calibration Clock Division
Bit 2 – DIFFPM Differential Pad Mode
| Value | Description |
|---|---|
| 0 | Pad differential mode is not enabled. |
| 1 | Pad differential mode is enabled. |
Bit 1 – DAPCAL Disable Automatic Pad Calibration
| Value | Description |
|---|---|
| 0 | Pad calibration is started automatically depending on the configuration of QSPI_REFRESH. |
| 1 | Pad calibration is not started automatically. |
Bit 0 – AAON Analog Always On
| Value | Description |
|---|---|
| 0 | The analog part of the pad calibration circuitry is switched off after each calibration (long delay for each calibration). |
| 1 | The analog part of the pad calibration circuitry is not switched off after each calibration (shorter delay after the first calibration). |