64.7.5 QSPI Interrupt Status Register

Name: QSPI_ISR
Offset: 0x10
Reset: 0x00000000
Property: Read-Only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       TOUTRFRSHD 
Access RR 
Reset 00 
Bit 15141312111098 
 CSRACSFAQITRQITFLWRAINSTRECSFCSR 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
     OVRESTXEMPTYTDRERDRF 
Access RRRR 
Reset 0000 

Bit 17 – TOUT QSPI Time-out (cleared by writing QSPI_CR.RTOUT)

ValueDescription
0 No QSPI time-out occurred.
1 At least one QSPI time-out occurred.

Bit 16 – RFRSHD Refresh Done (cleared on read)

ValueDescription
0 No ‘refresh done’ event occurred since the last read of QSPI_ISR.
1 One ‘refresh done’ event has been detected since the end of the last refresh command or the last read of QSPI_ISR.

Bit 15 – CSRA Chip Select Rise Autoclear

See Device Selection Flags.
ValueDescription
0 No chip select rise has been detected since beginning of the last command or the last read of QSPI_ISR.
1 One chip select rise has been detected since the beginning of the last command or the last read of QSPI_ISR.

Bit 14 – CSFA Chip Select Fall Autoclear

See Device Selection Flags.
ValueDescription
0 No chip select fall has been detected since end of the last command or the last read of QSPI_ISR.
1 One chip select fall has been detected since the end of the last command or the last read of QSPI_ISR.

Bit 13 – QITR QSPI Interrupt Rise (cleared on read)

ValueDescription
0 No rising of the QSPI memory interrupt line has been detected since the last read of QSPI_ISR.
1 At least one QSPI memory interrupt line rising edge occurred since the last read of QSPI_ISR.

Bit 12 – QITF QSPI Interrupt Fall (cleared on read)

ValueDescription
0 No falling of the QSPI memory interrupt line has been detected since the last read of QSPI_ISR.
1 At least one QSPI memory interrupt line falling edge occurred since the last read of QSPI_ISR.

Bit 11 – LWRA Last Write Access (cleared on read)

ValueDescription
0 Last write access has not been sent since the last read of QSPI_ISR or NBWRA=0.
1 At least one last write access has been sent since the last read of QSPI_ISR.

Bit 10 – INSTRE Instruction End Status (cleared on read)

ValueDescription
0 No instruction end has been detected since the last read of QSPI_ISR.
1 At least one instruction end has been detected since the last read of QSPI_ISR.

Bit 9 – CSF Chip Select Fall (cleared on read)

See Device Selection Flags.
ValueDescription
0 No chip select rise has been detected since the last read of QSPI_ISR.
1 At least one chip select rise has been detected since the last read of QSPI_ISR.

Bit 8 – CSR Chip Select Rise (cleared on read)

See Device Selection Flags.
ValueDescription
0 No chip select rise has been detected since the last read of QSPI_ISR.
1 At least one chip select rise has been detected since the last read of QSPI_ISR.

Bit 3 – OVRES Overrun Error Status (cleared on read)

An overrun occurs when QSPI_RDR is loaded at least twice from the serializer since the last read of the QSPI_RDR.

ValueDescription
0 No overrun has been detected since the last read of QSPI_ISR.
1 At least one overrun error has occurred since the last read of QSPI_ISR.

Bit 2 – TXEMPTY Transmission Registers Empty (cleared by writing QSPI_TDR)

TXEMPTY is set to zero when the QSPI is disabled or at reset. The QSPI enable command sets this bit to one.

ValueDescription
0 As soon as data is written in QSPI_TDR.
1 QSPI_TDR and the internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.

Bit 1 – TDRE Transmit Data Register Empty (cleared by writing QSPI_TDR)

TDRE is set to zero when the QSPI is disabled or at reset. The QSPI enable command sets this bit to one.

ValueDescription
0 Data has been written to QSPI_TDR and not yet transferred to the serializer.
1 The last data written in the QSPI_TDR has been transferred to the serializer.

Bit 0 – RDRF Receive Data Register Full (cleared by reading QSPI_RDR)

ValueDescription
0 No data has been received since the last read of QSPI_RDR.
1 Data has been received and the received data has been transferred from the serializer to QSPI_RDR since the last read of QSPI_RDR.