64.7.13 QSPI Instruction Frame Register

This register can only be written if the WPEN bit is cleared in the QSPI Write Protection Mode Register.

Name: QSPI_IFR
Offset: 0x38
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
  PROTTYP[2:0]HFWBENDDRCMDENDQSENAPBTFRTYP 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 2322212019181716 
 SMRMENDNBDUM[5:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 DDRENCRM TFRTYPADDRL[1:0]OPTL[1:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 76543210 
 DATAENOPTENADDRENINSTENWIDTH[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 30:28 – PROTTYP[2:0] Protocol Type

ValueNameDescription
0 STD_SPI Standard (Q)SPI protocol (to be selected if no other value matches the device)
1 TWIN_QUAD Twin-Quad protocol
2 OCTAFLASH OctaFlash protocol
3 HYPERFLASH HyperFlash protocol

Bit 27 – HFWBEN HyperFlash Write Buffer Enable

ValueDescription
0 No effect.
1 Each write access received on the system bus interface generates a new command.

Mandatory if the HyperFlash Write Buffer feature is used.

Bit 26 – DDRCMDEN DDR Mode Command Enable

ValueNameDescription
0 DISABLED Transfer of instruction field is performed in Single Data Rate mode even if DDREN is written to 1.
1 ENABLED Transfer of instruction field is performed in Double Data Rate mode if DDREN bit is written to 1. If DDREN is written to 0, the instruction field is sent in Single Data Rate mode.

Bit 25 – DQSEN DQS Sampling Enable

ValueDescription
0 Data from the memory are not sampled with the DQS signal.
1 Data from the memory are sampled with the DQS signal.

Bit 24 – APBTFRTYP Peripheral Bus Transfer Type

ValueDescription
0 Register transfer to the memory is a write transfer. Used when TRFTYP is written to 0 and SMRM to 1.
1 Register transfer to the memory is a read transfer. Used when TRFTYP is written to 0 and SMRM to 1.

Bit 23 – SMRM Serial Memory Register Mode

See Instruction Frame Transmission for details.
ValueDescription
0 Serial Memory registers are written via system bus access.
1 Serial Memory registers are written via peripheral bus access.

Bit 22 – END Endianness

ValueDescription
0 Data are sent in little-endian format to the memory.
1 Data are sent in big-endian format to the memory.

Bits 21:16 – NBDUM[5:0] Number Of Dummy Cycles

Defines the number of dummy cycles (also called read latency) required by the serial memory before data transfer.

Bit 15 – DDREN DDR Mode Enable

DDRCMDEN defines how the instruction field is sent when Double Data Rate mode is enabled. If DDRCMDEN is at 0, the instruction field is sent in Single Data Rate mode.
ValueNameDescription
0 DISABLED Transfers are performed in Single Data Rate mode.
1 ENABLED Transfers are performed in Double Data Rate mode, whereas the instruction field is still transferred in Single Data Rate mode.

Bit 14 – CRM Continuous Read Mode

ValueNameDescription
0 DISABLED Continuous Read mode is disabled.
1 ENABLED Continuous Read mode is enabled.

Bit 12 – TFRTYP Data Transfer Type

ValueNameDescription
0 TRSFR_REGISTER Read/Write of memory register, write of memory page buffer. This configuration implies the following:
  • Either the system bus or the peripheral bus can be used to initiate the transfer (SMRM bit).
  • If the peripheral bus is used, the RDRF and TDRE flags help to control the frame.
  • Scrambling is possible only for write accesses and if the peripheral bus is used.
  • For HyperFlash memories the “target” bit is set to register space in the HyperFlash header.
1 TRSFR_MEMORY Read/Write accesses to the memory space. This configuration implies the following:
  • Only the System Bus interface can be used to trigger accesses.
  • Access to random location is possible.
  • Address mask is applied and full system bus size accesses only are performed.
  • The internal optimization algorithm is enabled to minimize latency, and protocol specificities are handled automatically.
  • Seamless scrambling is possible.
  • Seamless handling of HyperFlash Write Buffer programming command (one command for each data)
  • Address shift is handled seamlessly (halfword memories, for example).

Bits 11:10 – ADDRL[1:0] Address Length

The ADDRL bit determines the length of the address.
ValueNameDescription
0 8_BIT 8-bit address size
1 16_BIT 16-bit address size
2 24_BIT 24-bit address size
3 32_BIT 32-bit address size

Bits 9:8 – OPTL[1:0] Option Code Length

Determines the length of the option code. The value written in OPTL must be consistent with the value written in the field WIDTH. For example, OPTL = 0 (1-bit option code) is not consistent with WIDTH = 6 (option code sent with the Quad SPI protocol, requiring a minimum length of 4 bits).
ValueNameDescription
0 OPTION_1BIT The option code is 1 bit long.
1 OPTION_2BIT The option code is 2 bits long.
2 OPTION_4BIT The option code is 4 bits long.
3 OPTION_8BIT The option code is 8 bits long.

Bit 7 – DATAEN Data Enable

ValueDescription
0 No data is sent/received to/from the serial Flash memory.
1 Data is sent/received to/from the serial Flash memory.

Bit 6 – OPTEN Option Enable

ValueDescription
0 The option is not sent to the serial Flash memory.
1 The option is sent to the serial Flash memory.

Bit 5 – ADDREN Address Enable

ValueDescription
0 The transfer address is not sent to the serial Flash memory.
1 The transfer address is sent to the serial Flash memory.

Bit 4 – INSTEN Instruction Enable

ValueDescription
0 The instruction is not sent to the serial Flash memory.
1 The instruction is sent to the serial Flash memory.

Bits 3:0 – WIDTH[3:0] Width of Instruction Code, Address, Option Code and Data

OCT_OUTPUT, OCT_IO and OCT_CMD are supported only in DDR mode (QSPI_IFR.DDREN must be set). However, the instruction code can still be sent in SDR or DDR mode depending on DDRCMDEN configuration.
ValueNameDescription
0 SINGLE_BIT_SPI Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI
1 DUAL_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI
2 QUAD_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI
3 DUAL_IO Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI
4 QUAD_IO Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI
5 DUAL_CMD Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI
6 QUAD_CMD Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI
7 OCT_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Octal SPI
8 OCT_IO Instruction: Single-bit SPI / Address-Option: Octal SPI / Data: Octal SPI
9 OCT_CMD Instruction: Octal SPI / Address-Option: Octal SPI / Data: Octal SPI