64.7.15 QSPI Scrambling Mode Register

This register can only be written if the WPEN bit is cleared in the QSPI Write Protection Mode Register.

Name: QSPI_SMR
Offset: 0x40
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      SCRKLRVDISSCREN 
Access R/WR/WR/W 
Reset 000 

Bit 2 – SCRKL Scrambling Key Lock

ValueDescription
0 No action.
1 QSPI_SKR.USRK cannot be written until the next VDDCORE reset.

Bit 1 – RVDIS Scrambling/Unscrambling Random Value Disable

ValueDescription
0 The scrambling/unscrambling algorithm includes the user scrambling key plus a random value that may differ between devices.
1 The scrambling/unscrambling algorithm includes only the user scrambling key.

Bit 0 – SCREN Scrambling/Unscrambling Enable

ValueNameDescription
0 DISABLED Scrambling/unscrambling is disabled.
1 ENABLED Scrambling/unscrambling is enabled.