64.7.21 QSPI Pad Calibration Bypass Register

This register can only be written if the WPEN bit is cleared in the QSPI Write Protection Mode Register.

This register is not affected by a software reset (QSPI_CR.SWRST).

Name: QSPI_PCALBP
Offset: 0x60
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     CALNBP[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
     CALPBP[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
        BPEN 
Access R/W 
Reset 0 

Bits 19:16 – CALNBP[3:0] Calibration Code Bypass for N-channel

Bits 11:8 – CALPBP[3:0] Calibration Code Bypass for P-channel

Bit 0 – BPEN Bypass Enable

ValueDescription
0 The calibration code is not overridden by values of CALNBP and CALPBP.
1 The calibration code is overridden by values of CALNBP and CALPBP.