13.4.8.1 Common Transfer Mode Sequence

Regardless of the transfer mode, all DMA transfers follow the same basic sequence:

  1. Upon the receipt of a DMA trigger or the setting of the CHREQ bit (DMAxCH[4]), data are loaded into DMABUF from the location addressed by DMAxSRC, then stored in the location addressed by DMAxDST.
  2. Following the transaction, DMAxSRC and DMAxDST are updated appropriately; one or both may be incremented or decremented, depending on the channel’s configuration (see Addressing Modes for additional information). At the same time, DMAxCNT is decremented by one.
  3. The module tests for any DMA interrupt conditions. If an interrupt condition has occurred, the DMAxSTAT register flags are updated accordingly:
    • If a DMA interrupt has occurred, all modes continue to step 4.
    • If an interrupt has not occurred, all modes return to step 1. In One-Shot mode, the controller waits for the next trigger. In Continuous mode, the controller repeats the cycle continuously until DMAxCNT value becomes 0 or a DMA interrupt occurs.
  4. If DMAxCNT has decremented to zero:
    • The values of DMAxSRC, DMAxDST and DMAxCNT are reloaded and the sequence repeats from step 1 (all Repeated modes).
    • The CHEN bit (DMAxCH[0]) is cleared and the channel is disabled (One-Shot and Continuous modes).
  5. If DMAxCNT has not decremented to zero, the controller checks for a memory address boundary violation of DMALOW or DMAHIGH:
    • If one of the boundaries has been crossed, the CHEN bit is cleared, and the channel is disabled.
    • If there is no boundary violation, the controller returns to step 1. For both One-Shot modes, the controller waits for the next trigger. For both Continuous modes, the controller proceeds to performing the next data transfer.

The four data transfer modes differ in the number of data transfers that can take place with a single trigger and how the DMAxCNT register behaves. The common logic flow for all data transfer modes is illustrated in the flowchart in Figure 13-4. The differences between the modes are summarized in Table 13-21.

Table 13-21. Comparison of DMA Data Transfer Modes
Transfer ModeTransfers per TriggerDMAxCNT Behavior
Decrements onat 0000h
One-ShotSingleTriggerDisable Channel
Repeated One-ShotTransferReload and Repeat
ContinuousMultipleTriggerDisable Channel
Repeated ContinuousTransferReload and Repeat
Figure 13-4. Common Logic Flow for Data Transfer Modes
Note: When CHEN = 1, in non-repeated modes (one-shot or continuous), the registers DMAxSRC, DMAxDST and DMATxCNT are reloaded based on their respective reload bits status (RELOADS, RELOADD and RELOADC).