4.4.5.7 Instruction RAM Configuration Sequence

The proper sequence for configuring and using IRAM is as follows:
  1. Write BMXIRAML/BMXIRAMH to ‘0’ to ensure no RAM locations are write protected. This step is optional if the sequence is done at Reset as both registers reset to a value of ‘0’.
  2. Copy instructions into desired RAM locations from Flash or other storage mechanism (e.g., bootloader).
  3. Set the IRAM start and end addresses by writing to the BMXIRAML and BMXIRAMH registers.
  4. Vector to any RAM location within the IRAM window to begin execution from RAM.

The BMXIRAML and BMXIRAMH registers are implemented with write protection to ensure that users have the ability to lock the designated IRAM range after configuration. The BMX does not support aborts on RAM accesses. The CPU will be responsible for ignoring unneeded instruction data delivered from the RAM access.

When switching from executing from NVM to executing from RAM, the following will occur:
  1. Any active NVM fetches would be aborted by the PBU. The new RAM instruction fetch will be immediately sent to the CPU as soon as data are available.
  2. To prevent cache thrashing, PBU is put into a ‘Standby’ state while running from RAM.