4.4.5.3 Target Bus Error Handling

A target will generate a bus error in any situation where it is unable to deliver data back to the BMX on a read event or unable to latch data on a write event. The target will retain relevant error status information which can be used to determine the cause of the bus error.

The BMX will set the Write Target Error bits or Read Target Error bits for the specific target that caused the error within the Error register for the initiator that generated the bus transaction.

For example, an ECC DED error on an XRAM read by the CPU would set the XRAMERR (BMXXDATERR) bit. Refer to Table 4-13 for target indices.