20.5.4.3.3 7-Bit Address and Client Write

After the Start condition, the module shifts 8 bits into the I2CxRSR register, as illustrated in Figure 20-23. The value of the I2CxRSR register is evaluated against that of the I2CxADD and I2CxMSK registers on the falling edge of the eighth clock (SCLx). If the address is valid (that is, an exact match between unmasked bit positions), the following events occur:

An ACK is generated if the AHEN bit is clear
The D/A and R/W status bits are cleared
The CLTACT (I2CxSTAT2[30]) bit is set
The module generates the I2CxIF interrupt on the falling edge of the ninth SCLx clock if CADDRIE (I2CxINTC[10]) bit and CSTIE(I2CxINTC[12]) are enabled
The module waits for the host to send data

Figure 20-23. Client Write 7-Bit Address Detection Timing Diagram