20.5.4.3.6 10-Bit Addressing Mode

In 10-Bit Addressing mode, the client must receive two device address bytes, as illustrated in Figure 20-28. The five MSbs of the first address byte specify a 10-bit address. The R/W status bit of the address must specify a write, causing the client device to receive the second address byte. For a 10-bit address, the first byte would equal, ‘11110 A9 A8 0’, where A9 and A8 are the two MSbs of the address.

The I2CxMSK register can mask any bit position in a 10-bit address. The 2 MSbs of the I2CxMSK register are used to mask the MSbs of the incoming address received in the first byte. The remaining byte of the register is then used to mask the lower byte of the address received in the second byte.

Following the Start condition, the module shifts eight bits into the I2CxRSR register. The value of the I2CxRSR[2:1] bits is evaluated against the value of the I2CxADD[9:8] and I2CxMSK[9:8] bits, while the value of the I2CxRSR[7:3] bits is compared to ‘11110’. Address evaluation occurs on the falling edge of the eighth SCLx clock. For the address to be valid, the I2CxRSR[7:3] bits must be equal to ‘11110’, while the I2CxRSR[2:1] bits must exactly match any unmasked bits in the I2CxADD[9:8] bits (if both bits are masked, a match is not needed). If the address is valid, the following events occur:

• An ACK is generated
• The D/A and R/W status bits are cleared
• The module generates the I2CxIF interrupt on the falling edge of the ninth SCLx clock if the CADDRIE (I2CxINTC[10]) bit and CSTIE(I2CxINTC[12]) are enabled.

The module does generate an interrupt after the reception of the first byte of a 10-bit address; however, this interrupt is of little use.

The module will continue to receive the second byte into the I2CxRSR register. This time, the I2CxRSR[7:0] bits are evaluated against the I2CxADD[7:0] and I2CxMSK[7:0] bits. If the lower byte of the address is valid, as previously described, the following events occur:

• An ACK is generated
• The ADD10 status bit is set
• The module generates the I2CxIF interrupt on the falling edge of the ninth SCLx clock if the CADDRIE (I2CxINTC[10]) bit and CSTIE (I2CxINTC[12]) are enabled.
• The module will wait for the host to send data or initiate a Repeated Start condition
  Note: Following a Repeated Start condition in 10-Bit Addressing mode, the client only matches the first 7-bit address, ‘11110 A9 A8 0’.