20.5.4.3.5 7-Bit Address and Client Read

When a client read is specified by having R/W = 1 in a 7-bit address byte, the process of detecting the device address is similar to that of a client write, as illustrated in Figure 20-26. If the addresses match, the following events occur:

• An ACK is generated if the AHEN bit is clear
• The D/A status bit is cleared and the R/W status bit is set
• The module generates the I2CxIF interrupt on the falling edge of the ninth SCLx clock if the CADDRIE (I2CxINTC[10]) bit and CSTIE(I2CxINTC[12]) are enabled

Because the client is expected to reply with data at this point, it is necessary to suspend the operation of the I²C bus to allow the user software to prepare a response. This is done automatically when the module clears the SCLREL bit. With SCLREL low, the client will pull down the SCLx clock line, causing a Wait on the I²C bus. The SSPND (I2CxSTAT2[31]) bit will be set by the hardware to indicate clock stretching. Packet size (PSZ, I2CxCON2[15:0]) and ND/A needs to be configured and then the user software writes the I2CxTRN register with the response data. SSPND (I2CxSTAT2[31]) bit will be automatically cleared by hardware. If Smart Mode (SMEN, I2CxCON2[17]) is disabled, the user must set SCLREL to release the clock or the hardware will automatically set SCLREL to release the clock.

Data setup time (TSU:DAT) can be configured by writing the required setup time to SDASUT(I2CXSDASUT[15:0]) and then enabling SDASUTEN (I2CXSDASUT[31]). In SMART mode (SMEN, I2CxCON2 [17]), hardware will automatically set SCLREL after data setup time.

Once packet size becomes zero, the end of packet (EOP) will be set (I2CxSTAT2[24]).