20.5.4.3.4 7-Bit Address and Client Write with the AHEN and DHEN Bits

The client device reception, with the AHEN and DHEN bits set, operates with extra interrupts and clock stretching added after the eighth falling edge of SCLx. These additional interrupts allow the client software to decide whether it wants to ACK the receive address or data byte rather than the hardware.

Note: The I2CxIF interrupt is still set after the ninth falling edge of the SCLx clock, even if there is no clock stretching and the RBF bit has been cleared. The I2CxIF interrupt is not asserted if a NACK is sent to the host.
Figure 20-24. I2C Client, 7-Bit Address, Reception (STREN = 0, AHEN = 1, DHEN = 1)
Figure 20-25. I2C Client, 7-Bit Address, Reception (STREN = 1, AHEN = 0, DHEN = 0)