4.9.2.7.1.1 MCUCR – MCU Control Register


Bit	7	6	5	4	3	2	1	0
	Reserved[4:0]					SPIIO	IVSEL	IVCE
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:3 – Reserved[4:0] PB7HS, PB7LS, PB4HS, PUD, ENPS

These bits are port-related and, therefore, not discussed here. For more details on the description of these bits, see Alternate Port Functions from Related Links.

Bit 2 – SPIIO SPI Interrupt Only

If the SPIIO bit is ‘1’, all interrupts are blocked except for the SPI interrupts SPI, SRX_FIFO and STX_FIFO. For all non-SPI interrupts, it is as if the I bit in SREG is cleared. This is designed to keep interrupt routines from other interrupting sources. To keep the SPI interface responsive even during interrupt execution, the SPI interrupt is still passed to the AVR.

Bit 1 – IVSEL Interrupt Vector Select

When the IVSEL bit is cleared (‘0’), the interrupt vectors are placed at the start of the ROM memory. When this bit is set (‘1’), the interrupt vectors are moved to the beginning of the bootloader Flash. See Fuse Low Byte from Related Links. To avoid unintentional changes of the interrupt vector tables, a special write procedure must be followed to change the IVSEL bit:

Write the interrupt vector change the enable (IVCE) bit to ‘1’.
Within four cycles, write the desired value to IVSEL while writing a ‘0’ to IVCE.

Interrupts are automatically disabled while this sequence is executed. Interrupts are disabled if the cycle IVCE is set and remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I bit in the status register is unaffected by automatic disabling.

Note: If interrupt vectors are placed in the bootloader section and boot lock bit BLB02 is programmed, interrupts are disabled while executing from the application section. If interrupt vectors are placed in the application section and boot lock bit BLB12 is programmed, interrupts are disabled while executing from the bootloader section. For more details on boot lock bits, see Memory Access via SPM/LPM from Related Links.

Bit 0 – IVCE Interrupt Vector Change Enable

The IVCE bit must be written to logic ‘1’ to enable changing the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit disables interrupts, as explained in the preceding description.

Name:	MCUCR
Offset:	0x00E
Reset:	0x00