4.4.3.8.1.15 EOTC1A – End of
Telegram Conditions 1 for Path A
This register is used
only for hardware-controlled automatic telegram reception. It stores the EOTCA settings
that are valid from the start of the reception until a wake check OK (RDSIFR.WCOA) is
detected. The sequencer state machine copies its content at the beginning of the
reception to the EOTCA register.
Note: The
bit descriptions are found at the EOTCA target
register.
Name:
EOTC1A
Offset:
0x0F5
Reset:
0x00
Bit
7
6
5
4
3
2
1
0
EOTBFE
RRFEA
TELREA
TMOFEA
MANFEA
SYTFEA
AMPFEA
CARFEA
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Bit 7 – EOTBFE
Bit 6 – RRFEA
Bit 5 – TELREA
Bit 4 – TMOFEA
Bit 3 – MANFEA
Bit 2 – SYTFEA
Bit 1 – AMPFEA
Bit 0 – CARFEA
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
