44.12 Frequency Digital Phase Locked Loop (FDPLL)

Table 44-13. Frequency Digital Phase Locked Loop (FDPLL) AC Electrical Specifications
AC CHARACTERISTICSStandard Operating Conditions: VDD & VDDIO 2.7V to 5.5V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp

Param. No.SymbolCharacteristicsMin.TypMax.UnitsConditions
FDPLL_5FDPLL_JitterFDPLL96M Period Jitter Pk-to-Pk (1, 2)1.4—4.2%VDD = VDDIO = 5.0v, fIN = 32.768 kHz from

XOSC32K, fOUT = 48 MHz

1—13.5%VDD = VDDIO = 5.0v, fIN = 32.768 kHz from

XOSC32K, fOUT = 96 MHz

FDPLL_71.4—4.8%VDD = VDDIO = 5.0v, fIN = 2 MHz from

XOSC, fOUT = 48 MHz

1—10.6%VDD = VDDIO = 5.0v, fIN = 2 MHz from

XOSC, fOUT = 96 MHz

Note:
  1. REFCLK for FDPLL96M is XOSC or XOSC32K.
  2. The provided jitter performance will be the best achieved on the device. Digital activity can increase jitter but is highly dependent on the application use model.