35.9.5 XDMAC Global Interrupt Disable Register
| Name: | XDMAC_GID |
| Offset: | 0x10 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ID6 | ID5 | ID4 | ID3 | ID2 | ID1 | ID0 | |||
| Access | W | W | W | W | W | W | W | ||
| Reset | – | – | – | – | – | – | – |
Bits 0, 1, 2, 3, 4, 5, 6 – ID XDMAC Channel x Interrupt Disable
| Value | Description |
|---|---|
| 0 | This bit has no effect. The Channel x Interrupt Mask bit (XDMAC_GIM.IMx) is not modified. |
| 1 | The corresponding mask bit is reset. The Channel x Interrupt Status register interrupt (XDMAC_GIS) is masked. |