35.9.7 XDMAC Global Interrupt Status Register
| Name: | XDMAC_GIS |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IS6 | IS5 | IS4 | IS3 | IS2 | IS1 | IS0 | |||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6 – IS XDMAC Channel x Interrupt Status
| Value | Description |
|---|---|
| 0 | This bit indicates that either the interrupt source is masked at the channel level or no interrupt is pending for channel x. |
| 1 | This bit indicates that an interrupt is pending for the channel x. |