35.9.19 XDMAC Channel x Interrupt Disable Register [x = 0..6]
| Name: | XDMAC_CID |
| Offset: | 0x54 + n*0x40 [n=0..6] |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ROID | WBEID | RBEID | FID | DID | LID | BID | |||
| Access | W | W | W | W | W | W | W | ||
| Reset | – | – | – | – | – | – | – |
Bit 6 – ROID Request Overflow Error Interrupt Disable Bit
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables request overflow error interrupt. |
Bit 5 – WBEID Write Bus Error Interrupt Disable Bit
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables bus error interrupt. |
Bit 4 – RBEID Read Bus Error Interrupt Disable Bit
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables bus error interrupt. |
Bit 3 – FID End of Flush Interrupt Disable Bit
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables end of flush interrupt. |
Bit 2 – DID End of Disable Interrupt Disable Bit
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables end of disable interrupt. |
Bit 1 – LID End of Linked List Interrupt Disable Bit
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables end of linked list interrupt. |
Bit 0 – BID End of Block Interrupt Disable Bit
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables end of block interrupt. |