35.9.9 XDMAC Global Channel Disable Register

Name:	XDMAC_GD
Offset:	0x20
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
		DI6	DI5	DI4	DI3	DI2	DI1	DI0
Access		W	W	W	W	W	W	W
Reset		–	–	–	–	–	–	–

Bits 0, 1, 2, 3, 4, 5, 6 – DI XDMAC Channel x Disable

Value	Description
0	This bit has no effect.
1	Disables channel x.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.