35.9.2 XDMAC Global Configuration Register
| Name: | XDMAC_GCFG |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BXKBEN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CGDISIF | CGDISFIFO | CGDISPIPE | CGDISREG | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 8 – BXKBEN Boundary X Kilobyte Enable
| Value | Description |
|---|---|
| 0 |
The 1 Kbyte boundary is used. |
| 1 |
The controller does not meet the AHB specification. |
Bit 3 – CGDISIF Bus Interface Clock Gating Disable
| Value | Description |
|---|---|
| 0 | The automatic clock gating is enabled for the system bus interface. |
| 1 | The automatic clock gating is disabled for the system bus interface. |
Bit 2 – CGDISFIFO FIFO Clock Gating Disable
| Value | Description |
|---|---|
| 0 | The automatic clock gating is enabled for the main FIFO. |
| 1 | The automatic clock gating is disabled for the main FIFO. |
Bit 1 – CGDISPIPE Pipeline Clock Gating Disable
| Value | Description |
|---|---|
| 0 | The automatic clock gating is enabled for the main pipeline. |
| 1 | The automatic clock gating is disabled for the main pipeline. |
Bit 0 – CGDISREG Configuration Registers Clock Gating Disable
| Value | Description |
|---|---|
| 0 | The automatic clock gating is enabled for the configuration registers. |
| 1 | The automatic clock gating is disabled for the configuration registers. |