11.5.2 Use Case 2: SRAM Test Mode

In addition to the test modes described in the Test Modes section, the CAN controller can be put into SRAM test mode. The CAN controller has a built-in RAM, which is protected by EDAC that is used to store the receive and transmit messages.

To support software based memory testing, the CAN controller is put into SRAM test mode. When this SRAM test mode is active, the CAN controller operation is disabled and transparent access from the host APB interface to all SRAM memory locations is available. SRAM test mode gets enabled or disabled by setting the CAN command bit[3] of the CAN_COMMAND register. For more information, see Command Register. SRAM test mode and CAN controller operation are mutually exclusive. Thus, SRAM test mode gets enabled when CAN controller is stopped and the CAN controller gets started when the SRAM test mode is stopped. In the SRAM test mode:

• Transparent read and write access to all SRAM memory locations is supported
• All message buffer write protect features are disabled
• Access to receive and transmit message buffer control registers is disabled

In SRAM test mode, the APB interface is used to access different SRAM address directly for test or initialization purposes. At power-up, SRAM is not initialized and any READ action to the memory locations would result in an ECC error if EDAC is enabled. Hence, putting the CAN controller into SRAM test mode enables initialization of the SRAM so ECC errors at power-up do not occur if EDAC is enabled.

The following table provides address mapping between the APB and SRAM addresses.