13.1 Features

SmartFusion 2 SPI peripherals support the following features:

  • Master and Slave modes
  • Selectable slaves up to 8
  • Configurable slave select operation
  • Configurable clock polarity
  • Separate transmit (Tx) and receive (Rx) FIFOs to reduce interrupt service loading
  • Processor controlled and PDMA controlled mode of data transfer

The following figure shows details of the Microcontroller Subsystem (MSS). The SPI peripherals are interfaced to the AHB bus matrix through the APB interfaces (APB_0 and APB_1).

Figure 13-1. Microcontroller Subsystem Showing SPI Peripherals