6.3 Register Map

The following table lists the AHB bus matrix control registers in the SYSREG block.

Table 6-9. AHB Bus Matrix Register Map
Register Name	Register Type	Flash Write Protect	Reset Source	Description
Master Weight Configuration Register 0	RW-P	Register	SYSRESET_N	Configures WRR master arbitration scheme for masters.
Master Weight Configuration Register 1	RW-P	Register	SYSRESET_N	Configures WRR master arbitration scheme for masters.
Security Configuration Register for Masters 0, 1, and 2	RO-U	N/A	SYSRESET_N	Security bits for masters 0, 1, and 2
Security Configuration Register for Masters 4, 5, and DDR_FIC	RO-U	N/A	SYSRESET_N	Security bits for masters 4, 5, and DDR_FIC
Security Configuration Register for Masters 3, 6, 7, and 8	RO-U	N/A	SYSRESET_N	Security bits for masters 3, 6, 7, and 8
Security Configuration Register for Master 9	RO-U	N/A	SYSRESET_N	Security bits for master 9
MSS External Status Register	SW1C	N/A	SYSRESET_N	AHB bus matrix error status. Writing a 1 clears the status.
eSRAM Configuration Register	RW-P	Register	SYSRESET_N	This register configures eSRAM.
eNVM Configuration Register	RW-P	Register	SYSRESET_N	This register configures eNVM parameters.
eSRAM Latency Configuration Register	RW-P	Register	SYSRESET_N	This register configures maximum latency for accessing eSRAM0/1 slave.
eNVM Remap Base Address Control Register	RW-P	Register	SYSRESET_N	This signal indicates the base address of the segment in eNVM, which is to be remapped to location 0H.
eNVM FPGA Fabric Remap Base Address Register	RW-P	Register	SYSRESET_N	Configures where eNVM is mapped in fabric master space.
MSS DDR Bridge Non-Bufferable Address Control Register	RW-P	Register	SYSRESET_N	This register indicates the base address of the non-bufferable address region.
MSS DDR Bridge Non-Bufferable Size Control Register	RW-P	Register	SYSRESET_N	This register indicates the size of the non-bufferable address region.
DDR Configuration Register	RW-P	Register	SYSRESET_N	This register configures DDR parameters.