47.10.5 USART Control Register (SPI_MODE)

This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.

Name:	FLEX_US_CR (SPI_MODE)
Offset:	0x200
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					RCS	FCS
Access					W	W
Reset					–	–


Bit	15	14	13	12	11	10	9	8
								RSTSTA
Access								W
Reset								–


Bit	7	6	5	4	3	2	1	0
	TXDIS	TXEN	RXDIS	RXEN	RSTTX	RSTRX
Access	W	W	W	W	W	W
Reset	–	–	–	–	–	–

Bit 19 – RCS Release SPI Chip Select

Applicable if USART operates in SPI Host mode (USART_MODE = 0xE):

Value	Description
0	No effect.
1	Releases the Client Select Line NSS (RTS pin).

Bit 18 – FCS Force SPI Chip Select

Applicable if USART operates in SPI Host mode (USART_MODE = 0xE):

Value	Description
0	No effect.
1	Forces the Client Select Line NSS (RTS pin) to 0, even if USART is not transmitting, in order to address SPI client devices supporting the CSAAT mode (Chip Select Active After Transfer).

Bit 8 – RSTSTA Reset Status Bits

Value	Description
0	No effect.
1	Resets the FLEX_US_CSR.OVRE/UNRE status bits.

Bit 7 – TXDIS Transmitter Disable

Value	Description
0	No effect.
1	Disables the transmitter.

Bit 6 – TXEN Transmitter Enable

Value	Description
0	No effect.
1	Enables the transmitter if TXDIS is 0.

Bit 5 – RXDIS Receiver Disable

Value	Description
0	No effect.
1	Disables the receiver.

Bit 4 – RXEN Receiver Enable

Value	Description
0	No effect.
1	Enables the receiver, if RXDIS is 0.

Bit 3 – RSTTX Reset Transmitter

Value	Description
0	No effect.
1	Resets the transmitter.

Bit 2 – RSTRX Reset Receiver

Value	Description
0	No effect.
1	Resets the receiver.