47.10.7 USART Mode Register (SPI_MODE)
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
| Name: | FLEX_US_MR (SPI_MODE) |
| Offset: | 0x204 |
| Reset: | 0xC0000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WRDBT | CPOL | ||||||||
| Access | R/W | R/W | |||||||
| Reset | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CHMODE[1:0] | CPHA | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | – | – | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHRL[1:0] | USCLKS[1:0] | USART_MODE[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | – | 0 | – | 0 | 0 | 0 | – | |
Bit 20 – WRDBT Wait Read Data Before Transfer
| Value | Description |
|---|---|
| 0 | The character transmission starts as soon as a character is written into FLEX_US_THR (assuming TXRDY was set). |
| 1 | The character transmission starts when a character is written and only if RXRDY flag is cleared (Receive Holding Register has been read). |
Bit 16 – CPOL SPI Clock Polarity
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required clock/data relationship between host and client devices.
Applicable if USART operates in SPI mode (client or host, USART_MODE = 0xE or 0xF):
| Value | Description |
|---|---|
| 0 | The inactive state value of SPCK is logic level zero. |
| 1 | The inactive state value of SPCK is logic level one. |
Bits 15:14 – CHMODE[1:0] Channel Mode
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL | Normal mode |
Bit 8 – CPHA SPI Clock Phase
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between host and client devices.
Applicable if USART operates in SPI mode (USART_MODE = 0xE or 0xF):
| Value | Description |
|---|---|
| 0 | Data are changed on the leading edge of SPCK and captured on the following edge of SPCK. |
| 1 | Data are captured on the leading edge of SPCK and changed on the following edge of SPCK. |
Bits 7:6 – CHRL[1:0] Character Length
| Value | Name | Description |
|---|---|---|
| 3 | 8_BIT | Character length is 8 bits |
Bits 5:4 – USCLKS[1:0] Clock Selection
| Value | Name | Description |
|---|---|---|
| 0 | MCK | Peripheral clock is selected |
| 1 | DIV | Peripheral clock Divided (DIV= 8) is selected |
| 2 | GCLK | A PMC generic clock is selected |
| 3 | SCK | External pin SCK is selected |
Bits 3:0 – USART_MODE[3:0] USART Mode of Operation
| Value | Name | Description |
|---|---|---|
| 0xE | SPI_MASTER | SPI host |
| 0xF | SPI_SLAVE | SPI client |