47.10.68 TWI Interrupt Enable Register
This register can only be written if the WPITEN bit is cleared in the TWI Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Name: | FLEX_TWI_IER |
Offset: | 0x624 |
Reset: | – |
Property: | Write-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | SMBHHM | SMBDAM | PECERR | TOUT | | MCACK | |
Access | | | W | W | W | W | | W | |
Reset | | | – | – | – | – | | – | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TXBUFE | RXBUFF | ENDTX | ENDRX | EOSACC | SCL_WS | ARBLST | NACK | |
Access | W | W | W | W | W | W | W | W | |
Reset | – | – | – | – | – | – | – | – | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UNRE | OVRE | GACC | SVACC | | TXRDY | RXRDY | TXCOMP | |
Access | W | W | W | W | | W | W | W | |
Reset | – | – | – | – | | – | – | – | |
Bit 21 – SMBHHM SMBus Host Header Address Match Interrupt Enable
Bit 20 – SMBDAM SMBus Default Address Match Interrupt Enable
Bit 19 – PECERR PEC Error Interrupt Enable
Bit 18 – TOUT Timeout Error Interrupt Enable
Bit 16 – MCACK Host Code Acknowledge Interrupt
Enable
Bit 15 – TXBUFE Transmit Buffer Empty Interrupt Enable
Bit 14 – RXBUFF Receive Buffer Full Interrupt Enable
Bit 13 – ENDTX End of Transmit Buffer Interrupt Enable
Bit 12 – ENDRX End of Receive Buffer Interrupt Enable
Bit 11 – EOSACC End Of Client Access Interrupt
Enable
Bit 10 – SCL_WS Clock Wait State Interrupt Enable
Bit 9 – ARBLST Arbitration Lost Interrupt Enable
Bit 8 – NACK Not Acknowledge Interrupt Enable
Bit 7 – UNRE Underrun Error Interrupt Enable
Bit 6 – OVRE Overrun Error Interrupt Enable
Bit 5 – GACC General Call Access Interrupt Enable
Bit 4 – SVACC Client Access Interrupt
Enable
Bit 2 – TXRDY Transmit Holding Register Ready Interrupt Enable
Bit 1 – RXRDY Receive Holding Register Ready Interrupt Enable
Bit 0 – TXCOMP Transmission Completed Interrupt Enable