26.4.5 Asynchronous Clock Counter Mode

When TCS bit = 1, ON bit = 1 and TSYNC bit = 0 in TxCON register, the timer increments on every rising edge of the applied external clock signal. The timer counts up to a match value preloaded in the respective period register, then rolls over and continues. This incrementing sequence repeats until the timer is disabled (refer to Figure 26-5).

Figure 26-5. Asynchronous External Clock Mode Timing Diagram

When the timer is configured for asynchronous operation and the CPU goes into Idle mode with SIDL bit = 1 or sleep, the timer continues incrementing.