26.4.2 Synchronous External Clock Counter Mode

When TCS bit = 1, ON bit = 1 and TSYNC bit = 1 in the TxCON register, the timer increments on the synchronized rising edge of the applied external clock (TxCK pin) signal. The synchronization of the input signal occurs with the System Clock signal. The timer counts up to a match value preloaded in the period register, then resets and continues. This incrementing sequence repeats until the timer is disabled (refer to Figure 26-3).

Figure 26-3. Synchronized External Clock Mode Timing Diagram

When the CPU goes into Sleep mode, or when the timer is configured for the Synchronous mode of operation and the CPU goes into Idle mode with SIDL bit = 1, the timer will stop incrementing. The timer module logic will resume the incrementing sequence upon termination of the CPU Idle/Sleep mode. If SIDL bit = 0 in TxCON register, the timer will continue to operate.