When TCS bit = 0 and ON bit = 1 in the TxCON register,
the timer increments on every rising edge of the system clock up to a match value,
preloaded into the period register PRx, then rolls over and continues. The use of period
registers allows for any timer value to be reached as the maximum while providing a
specific period/time interval to be repeated with no firmware intervention (refer to Figure 26-2). Figure 26-2. Synchronous Clock Counter Mode
Timing Diagram (1:1 Prescale)
For the maximum timer period, load the period register with 0xFFFF_FFFF. This incrementing
sequence repeats until the timer is disabled by being turned off (ON (TxCON[15]) =
0), stopped in Idle (SIDL bit = 1) or the System Clock
is turned off (Sleep mode). The timer count is not reset when the module is turned off.
When the CPU goes into Sleep mode or Idle mode with SIDL (TxCON[13]) = 1,
the timer will stop incrementing. The timer module logic will resume the incrementing
sequence upon termination of the CPU Idle or Sleep mode. If the CPU goes into Idle mode
with SIDL bit = 0, the timer will continue to operate normally.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
