26.4.3 Gated Timer Mode

The timer can be placed in Gated Time Accumulation Operational mode to enable the timer clock source when the gate signal is asserted high. The Timer Control bit TGATE in TxCON register must be set to enable this mode. The timer must be enabled, ON bit (TxCON[15]) = 1 (refer to Figure 26-4).

When configured for this mode, gate operation starts on a rising edge of the signal applied to the TxCK input and terminates on the falling edge of the signal applied to the T1CK input. The timer will increment while the external gate signal is high. The gate signal must have a minimum high and low time greater than the timer input clock period to ensure that the TxCK input will have sufficient setup time to be sampled by the rising edge of the clock. The edges of the gate signal may occur asynchronously to the timer clock source.

The falling edge of the gate signal generates an interrupt. The latency of the interrupt is one to two time clock cycles after the falling edge. If TGATE = 1, TxCK = 0 and TON is set, an interrupt will be generated despite no falling edge existing on the gate input. The falling edge of the TxCK terminates the count operation, but does not reset the timer. The user must reset the timer if desiring to start from zero.