34.2.3 Deadman Timer Clear Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | DMTCLR |
| Offset: | 0x3A08 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| STEP2[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – STEP2[7:0] Clear Enable bits
| Value | Description |
|---|---|
| 00001000b | Clears STEP1 (DMTPRECLR[15:8]), STEP2 (DMTCLR[7:0]), and the Deadman Timer (STEP2) if, and only if, preceded by correct loading of the Preclear Enable bits (STEP1) in the correct sequence. The write to the STEP2 bits field may be verified by reading DMTCNT and observing the counter being reset. |
| All other write patterns | Sets BAD2 Flag; the value in the STEP1 bits will remain unchanged and the new value being written to the STEP2 bits will be captured. |