34.2.4 Deadman Timer Status Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | DMTSTAT |
| Offset: | 0x3A0C |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BAD1 | BAD2 | DMTEVENT | WINOPN | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 7 – BAD1 BAD STEP1 Value Detect bit
This bit is cleared by a Reset or a successful post NMI clear sequence bit.
| Value | Description |
|---|---|
| 1 | Incorrect STEP1[7:0] value was detected |
| 0 | Incorrect STEP1[7:0] value was not detected |
Bit 6 – BAD2 BAD STEP2 Value Detect bit
This bit is cleared by a Reset or a successful post NMI clear sequence bit.
| Value | Description |
|---|---|
| 1 | Incorrect STEP2[7:0] value was detected |
| 0 | Incorrect STEP2[7:0] value was not detected |
Bit 5 – DMTEVENT Deadman Timer Event bit
This bit is cleared by a Reset or a successful post NMI clear sequence bit.
| Value | Description |
|---|---|
| 1 | DMT counter expired, or a BAD1 or BAD2 step occurred |
| 0 | No errors detected |
Bit 0 – WINOPN Deadman Timer Clear Window bit
| Value | Description |
|---|---|
| 1 | Deadman Timer clear window is open |
| 0 | Deadman Timer clear window is not open |