35.2.3 Peripheral Module Disable 2 Register

Table 35-3. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	PMD2
Offset:	0x3A48


Bit	31	30	29	28	27	26	25	24
					CLC4MD	CLC3MD	CLC2MD	CLC1MD
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	23	22	21	20	19	18	17	16
								DACMD
Access								R/W
Reset								0


Bit	15	14	13	12	11	10	9	8
								DMAMD
Access								R/W
Reset								0


Bit	7	6	5	4	3	2	1	0
			SENT2MD	SENT1MD			I2C2MD	I2C1MD
Access			R/W	R/W			R/W	R/W
Reset			0	0			0	0

Bit 27 – CLC4MD CLC 4 Module Disable bit

Value	Description
1	CLC 4 module is disabled
0	CLC 4 module is enabled

Bit 26 – CLC3MD CLC 3 Module Disable bit

Value	Description
1	CLC 3 module is disabled
0	CLC 3 module is enabled

Bit 25 – CLC2MD CLC 2 Module Disable bit

Value	Description
1	CLC 2 module is disabled
0	CLC 2 module is enabled

Bit 24 – CLC1MD CLC 1 Module Disable bit

Value	Description
1	CLC 1 module is disabled
0	CLC 1 module is enabled

Bit 16 – DACMD Comparator 1 Module Disable bit

Value	Description
1	CMP1 Module is disabled
0	CMP1 Module is enabled

Bit 8 – DMAMD DMA Module Disable bit

Value	Description
1	DMA module is disabled
0	DMA module is enabled

Bit 5 – SENT2MD SENT 2 Module Disable bit

Value	Description
1	SENT 2 module is disabled
0	SENT 2 module is enabled

Bit 4 – SENT1MD SENT 1 Module Disable bit

Value	Description
1	SENT 1 module is disabled
0	SENT 1 module is enabled

Bit 1 – I2C2MD I²C 2 Module Disable bit

Value	Description
1	I²C 2 module is disabled
0	I²C 2 module is enabled

Bit 0 – I2C1MD I²C 1 Module Disable bit

Value	Description
1	I²C 1 module is disabled
0	I²C 1 module is enabled

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