35.2.5 Peripheral Module Disable 4 Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | PMD4 |
| Offset: | 0x3A50 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CM4MD | CM3MD | CM2MD | CM1MD | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PWMMD | IOIM4MD | IOIM3MD | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IOIM2MD | IOIM1MD | DMTMD | CRCMD | PTGMD | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 19 – CM4MD Clock Monitor 4 Disable bit
| Value | Description |
|---|---|
| 1 | Clock monitor 4 module is disabled |
| 0 | Clock monitor 4 module is enabled |
Bit 18 – CM3MD Clock Monitor 3 Disable bit
| Value | Description |
|---|---|
| 1 | Clock monitor 3 module is disabled |
| 0 | Clock monitor 3 module is enabled |
Bit 17 – CM2MD Clock Monitor 2 Disable bit
| Value | Description |
|---|---|
| 1 | Clock monitor 2 module is disabled |
| 0 | Clock monitor 2 module is enabled |
Bit 16 – CM1MD Clock Monitor 1 Disable bit
| Value | Description |
|---|---|
| 1 | Clock monitor 1 module is disabled |
| 0 | Clock monitor 1 module is enabled |
Bit 10 – PWMMD PWM Module Disable bit
| Value | Description |
|---|---|
| 1 | PWM module is disabled |
| 0 | PWM module is enabled |
Bit 9 – IOIM4MD IO Integrity Monitor 4 Disable bit
| Value | Description |
|---|---|
| 1 | IO integrity monitor 4 module is disabled |
| 0 | IO integrity monitor 4 module is enabled |
Bit 8 – IOIM3MD IO Integrity Monitor 3 Disable bit
| Value | Description |
|---|---|
| 1 | IO integrity monitor 3 module is disabled |
| 0 | IO integrity monitor 3 module is enabled |
Bit 7 – IOIM2MD IO Integrity Monitor 2 Disable bit
| Value | Description |
|---|---|
| 1 | IO integrity monitor 2 module is disabled |
| 0 | IO integrity monitor 2 module is enabled |
Bit 6 – IOIM1MD IO Integrity Monitor 1 Disable bit
| Value | Description |
|---|---|
| 1 | IO integrity monitor 1 module is disabled |
| 0 | IO integrity monitor 1 module is enabled |
Bit 2 – DMTMD DMT Module Disable bit
| Value | Description |
|---|---|
| 1 | CLC6 module is disabled |
| 0 | CLC6 module is enabled |
Bit 1 – CRCMD CRC Module Disable bit
| Value | Description |
|---|---|
| 1 | CRC module is disabled |
| 0 | CRC module is enabled |
Bit 0 – PTGMD PTG Module Disable bit
| Value | Description |
|---|---|
| 1 |
PTG module is disabled |
| 0 |
PTG module is enabled |