35.2.2 Peripheral Module Disable 1 Register

Table 35-2. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Gray cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
CWrite to clearSSoftware settable bitxChannel number
Name: PMD1
Offset: 0x3A44

Bit 3130292827262524 
      SPI3MDSPI2MDSPI1MD 
Access R/WR/WR/W 
Reset 000 
Bit 2322212019181716 
      U3MDU2MDU1MD 
Access R/WR/WR/W 
Reset 000 
Bit 15141312111098 
     T1MD    
Access R/W 
Reset 0 
Bit 76543210 
     CCP4MDCCP3MDCCP2MDCCP1MD 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 26 – SPI3MD SPI3 Module Disable bit

ValueDescription
1

SPI3 module is disabled

0

SPI3 module is enabled

Bit 25 – SPI2MD SPI2 Module Disable bit

ValueDescription
1

SPI2 module is disabled

0

SPI2 module is enabled

Bit 24 – SPI1MD SPI1 Module Disable bit

ValueDescription
1

SPI1 module is disabled

0

SPI1 module is enabled

Bit 18 – U3MD UART3 Module Disable bit

ValueDescription
1

UART3 module is disabled

0

UART3 module is enabled

Bit 17 – U2MD UART2 Module Disable bit

ValueDescription
1

UART2 module is disabled

0

UART2 module is enabled

Bit 16 – U1MD UART1 Module Disable bit

ValueDescription
1

UART1 module is disabled

0

UART1 module is enabled

Bit 11 – T1MD Timer 1 Module Disable bit

ValueDescription
1

Timer 1 module is disabled

0

Timer 1 module is enabled

Bit 3 – CCP4MD CCP 4 Module Disable bit

ValueDescription
1

CCP 4 module is disabled

0

CCP 4 module is enabled

Bit 2 – CCP3MD CCP 3 Module Disable bit

ValueDescription
1

CCP 3 module is disabled

0

CCP 3 module is enabled

Bit 1 – CCP2MD CCP 2 Module Disable bit

ValueDescription
1

CCP 2 module is disabled

0

CCP 2 module is enabled

Bit 0 – CCP1MD CCP 1 Module Disable bit

ValueDescription
1

CCP 1 module is disabled

0

CCP 1 module is enabled