27.4.2.1 Dual 16-Bit Timer Mode

Dual 16-Bit Timer mode is selected when T32 = 0. This mode is useful for the following functions:
  • CCPxTMR Periodic CPU Interrupts
  • Master Time Base Function for Synchronizing Other CCP Modules
  • Triggering Periodic A/D Conversion
  • Periodic Wake from Sleep (if an Appropriate Clock Source is Available)
Note: The CCPxTMRH/L register bit locations may not be readable by the user if a high-speed asynchronous clock source is used to clock the time base. For a low-speed read, a double read can be done and the results compared.

Dual 16-Bit Timer mode provides a simple timer function with two independent 16-bit timer/counters, as shown in Figure 27-3. The primary timer, based on the lower word of the CCPxTMR, is fully functional and can interact with other modules on the device. It can generate the CCP Sync signals for use by other CCP modules. It can also use the SYNC[4:0] signal generated by other modules. The secondary timer, based on the upper word of CCPxTMR, has limited functionality. It is intended to be used only as a periodic interrupt source for scheduling CPU events. It does not generate an output trigger signal like the primary time base.

Figure 27-3. 16-Bit Dual Timer Mode

Both the primary and secondary timers use the same clock source from the TBG, as selected by CLKSEL[2:0]. The CCPxTMRH/L register bit locations provide user access to the two 16-bit time bases. Both timer register bit locations (CCPxTMRL and CCPxTMRH) increment at the same time based on the timer input; however, only the primary timer (CCPxTMRL) can use the timer Sync functionality. The secondary timer (CCPxTMRH) does not have timer Sync functionality.

The CCPxPRL register bit locations control the period for the primary 16-bit time base when SYNC[4:0] = 00000. When the module is configured to use an external synchronization source, the primary 16-bit time base is reset when the source selected by SYNC[4:0] is asserted. The module’s Sync signal is generated whenever the time base rolls over or is reset to ‘0’.

The primary timer can generate the CCP interrupt when the value of CCPxTMRL resets to 0000h. When SYNC[4:0] = 00000, this occurs when CCPxTMRL matches CCPxPRL. If SYNC[4:0] is not ‘00000’, CCPxTMRL resets and generates a CCT Interrupt Flag (CCTxIF) event whenever the signal selected by SYNC[4:0] is asserted.

The CCPxPRH register bit locations control the count period of the secondary 16-bit timer. The secondary timer does not support external synchronization and is not affected by the selected SYNC[4:0] input. The secondary time base begins counting when the CCPON bit (CCPxCON1[15]) is set. When a match occurs between the CCPxPRH register bit locations and the CCPxTMRH count value, the secondary 16-bit time base is reset and a timer rollover interrupt event (CCPxIF) is generated.

If either of the 16-bit timers is not used in the application, the timer can be disabled by writing 0000h to the corresponding period register. The timer is held in Reset, and no interrupts are generated as long as the period register’s value is ‘0’. The CCPxPRH and CCPxPRL register bit locations are not buffered in this operating mode.

To use the module in Dual 16-Bit Timer mode:
  1. Set CCSEL = 0 to select the Time Base/Output Compare mode of the module.
  2. Set T32 = 0 to select the 16-bit time base operation.
  3. Set MOD[3:0] = 0000 to select the Time Base mode.
  4. Set SYNC[4:0] to the desired time base synchronization source:
    • Configure and enable the external source selected by SYNC[4:0] before enabling the timer.
    • If the timer is not using an external Sync source (SYNC[4:0] = 00000), or if the module is synchronizing to itself (the SYNC[4:0] bits select the module’s own value as a Sync source), write the desired count period of the primary 16-bit time base to CCPxPRL.
  5. If the secondary timer is also being used, write a non-zero value to CCPxPRH to specify the count period.
  6. If the special A/D trigger is being used, set CCPxRB for the desired trigger output time.
  7. Enable the module by setting the CCPON bit.
  8. If an external synchronization source is selected in step four, configure and enable that source to allow the primary 16-bit time base to begin counting.