27.4.2.3 Clock Gating for Timer Modes

When operating in Timer mode, time base gating can be used to gate the timer’s operation (see Gating Logic for more information). This function provides a simple way to measure the time of an external event. Timer clock gating is enabled whenever one or more of the ASDG[7:0] bits (CCPxCON2[7:0]) is set or when the SSDG bit (CCPxCON2[12]) is set.