11.2.9 Peripheral Access Control Register 2
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | PACCON2 |
| Offset: | 0x1E84 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MBISTCONWR | RPCONWR | WDTCONWR | CM2RANGEWR | CM2CONWR | CM3RANGEWR | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MBISTCONLK | RPCONLK | WDTCONLK | CM4RANGELK | CM4CONLK | CM3RANGELK | ||||
| Access | S/R | S/R | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 1 | 1 | 1 | 1 |
Bit 22 – MBISTCONWR MBIST Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable |
| 0 | Register is not writable |
Bit 20 – RPCONWR Peripheral Remapping Configuration Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable |
| 0 | Register is not writable |
Bit 19 – WDTCONWR Watchdog Timer Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable |
| 0 | Register is not writable |
Bit 18 – CM2RANGEWR Clock Monitor 2 Range (CM2WINPR - CM2LWARN) Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable |
| 0 | Register is not writable |
Bit 17 – CM2CONWR Clock Monitor 2 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable |
| 0 | Register is not writable |
Bit 16 – CM3RANGEWR Clock Monitor 3 Range (CM3WINPR - CM3LWARN) Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable |
| 0 | Register is not writable |
Bit 6 – MBISTCONLK MBIST Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked |
| 0 | Register is not write locked |
Bit 4 – RPCONLK Peripheral Remapping Configuration Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked |
| 0 | Register is not write locked |
Bit 3 – WDTCONLK Watchdog Timer Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is writable |
| 0 | Register is not writable |
Bit 2 – CM4RANGELK Clock Monitor 4 Range (CM4WINPR - CM4LWARN) Lock bit
| Value | Description |
|---|---|
| 1 | Register is writable |
| 0 | Register is not writable |
Bit 1 – CM4CONLK Clock Monitor 4 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is writable |
| 0 | Register is not writable |
Bit 0 – CM3RANGELK Clock Monitor 3 Range (CM3WINPR - CM3LWARN) Lock bit
| Value | Description |
|---|---|
| 1 | Register is writable |
| 0 | Register is not writable |
Bit 0 – IOIM12CONWR IOIM 12 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable |
| 0 | Register is not writable |