11.2.2 IRT Control Register

Note:

Register is read-only when PLCK bit is set.
If the PLCK bit is set, then access to the IRT regions is disabled, and the IRTCTRL and IRTSTAT registers are read-only.
DBG bit controls debug access to the IRT partition when the IRT is enabled.
EAA controls the external access via debug and ICSP interfaces when IRT and secure debug are enabled. Setting the EAA bit allows debug and ICSP programmer access; otherwise, these functions are disabled.

Table 11-2. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	IRTCTRL
Offset:	0x2E4


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
			IACT	PLCK		DONE	DBG	EAA
Access			R/HS	R/HS		R/S	R/W	R/W
Reset			0	0		0	0	0

Bit 5 – IACT

Value	Description
1
0

Bit 4 – PLCK IRT Partition Lock Status bit ^(1,2)

Value	Description
1	IRT partition is locked
0	IRT partition is not locked

Bit 2 – DONE UCA Write Protect Enable bit

Write 1 to set; Writing 0 has no effect

Value	Description
1	IRT execution is done
0	IRT execution is not finished

Bit 1 – DBG IRT Debug Enable bit ⁽³⁾

Reset on POR or BOR only

Value	Description
1	Debug access to IRT partition is allowed
0	Debug access to IRT partition is disabled

Bit 0 – EAA External Access (Debugger or Programmer) Enable Bit⁽⁴⁾

Reset on POR or BOR only

Value	Description
1	External access for debug, programming and test interfaces is enabled
0	External access for debug, programming and test interfaces is disabled

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