13.6.1 INTCON1 through INTCON5

Global interrupt control functions are controlled from INTCON1 through INTCON5. INTCON1 contains the Interrupt Nesting Disable bit (NSTDIS), Global Interrupt Enable bit (GIE) and the status flags for the processor trap sources.

The INTCON2 register controls the external interrupt polarity select bits. INTCON3 contains the status flags for the different bus error traps and INTCON4 contains control and status flags for various math error traps.

INTCON5 contains the Soft Trap bit and other generic trap bits associated with WDT, DMT events, XRAM and YRAM PWB DED Error status.