13.6.5 INTTREG

When an interrupt is presented to the CPU, associated details of the interrupt are latched onto the INTTREG register. INTTREG[IRQCPU] represents the interrupt IRQ request status, while INTTREG[ILR] holds the priority level of the presented interrupt. If INTTREG[VHOLD] is equal to 1, the value of INTTREG[VECNUM] represents the vector number of the presented interrupt. Otherwise, it represents the vector number of the last acknowledged interrupt.

INTTREG holds the value of ILR and VECNUM, until the next interrupt in presented to the CPU.

The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence as they are listed in Table 13-1. For example, the FPU exception is shown as having a vector number of 10 and an IRQ number of 1. Thus, the FPUIF bit is placed at IFS0[1], the FPUIE bit in IEC0[1] and FPUIP[2:0] bits in IPC0(IPC0[6:4]).

Note: The lower the IRQ number, the higher its natural order priority. Therefore, when two simultaneous interrupts occur with the same user-assigned priority, the one with the lower IRQ number will be given precedence.