1.3.1 Design Data Flow

The demo design performs the following control plane operations:

• LED Blink: Host PC driver performs BAR2 MWr operation to EndPoint. The PCIe controller generates AXI write transaction on AXI_IO_CTRL logic’s to blink LEDs.
• DIP Switch Read: Host PC driver performs BAR2 MRd to EndPoint. The PCIe controller generates AXI read transaction on AXI_IO_CTRL logic’s to blink LEDs.
• MSI Interrupt Count: When on-board push button is pressed, the PCIe EndPoint generates interrupt to host PC and the host PC driver increments the corresponding interrupt counter.
• Memory Read/Write: Host PC driver configures the ATR2 translation address to DDR3L/DDR4/LSRAM base address. It performs BAR2 memory read/write transactions to DDR3L/DDR4/LSRAM memories.

The demo design supports the following types of DMA operations.

• Continuous DMA operations
• SGDMA Operations
• Core DMA Operations