1.3.2 Design Implementation

The following figure shows the Libero SoC software top-level design implementation of the PCIe EndPoint reference design.

Figure 1-4. PCIe EndPoint Reference Design

The top-level design includes the following SmartDesign components, memory controller subsystems and AXI4Interconnect IP:

  • PCIe EP subsystem
  • CoreDMA and UART subsystem
  • AXItoAPB
  • DDR3L subsystem
  • DDR4 subsystem
  • AXI LSRAM
  • AXI4Interconnect IP