13.4.47 ADC Early Interrupt Status Register High
| Name: | ADEISTATH |
| Offset: | 0xBFA |
Legend: R = Readable bit; HS = Hardware Settable bit; HC = Hardware Clearable bit
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EISTAT[31:24] | |||||||||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EISTAT[23:16] | |||||||||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – EISTAT[31:16] Early Interrupt Status for Corresponding Analog Input bits
Note: EISTAT[x] is cleared upon a corresponding ADCBUFx
read.
| Value | Description |
|---|---|
1 |
Early interrupt was generated |
0 |
Early interrupt was not generated since the last ADCBUFx read |