40.6.1 Network Control Register

Writing one to this bit halts transmission as soon as any ongoing frame transmission ends.

Writing one to this bit starts transmission.

If set in half duplex mode, forces collisions on all received frames.

Setting this bit to one makes the statistics registers writable for functional test purposes.

This bit is write only. Writing a one increments all the statistics registers by one for test purposes.

This bit is write only. Writing a one clears the statistics registers.

When set, enables the Ethernet transmitter to send data. When reset transmission, stops immediately, the transmit FIFO and control registers are cleared and the EMAC_TBQP register resets to point to the start of the transmit descriptor list.

When set, enables the EMAC to receive data. When reset, frame reception stops immediately and the receive FIFO is cleared. The EMAC_RBQP register is unaffected.

Connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with MCK divided by 4. rx_clk and tx_clk may glitch as the EMAC is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back.

Asserts the loopback signal to the PHY.