40.6.14 EMAC Statistics Registers

EMAC_PFR is an EMAC statistics register. It resets to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.

Name:	EMAC_PFR
Offset:	0x3C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	FROK[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	FROK[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:0 – FROK[15:0] Pause Frames Received OK

A 16-bit register counting the number of good pause frames received. A good frame has a length of 64 to 1518 (1536 if bit 8 set in EMAC_NCFGR) and has no FCS, alignment or receive symbol errors.